1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, especially to a semiconductor integrated circuit device in which degrees of freedom of the design can be improved.
2. Description of the Related Art
In the design of a semiconductor integrated circuit device, arrangement locations of an I/O buffer area and a gate area are previously determined. For example, the I/O buffer area is in the circumferential portion of a chip where the semiconductor integrated circuit device is formed, and the gate area is in the center portion of the chip surrounded by the I/O buffer area. I/O buffers, basic cells, and macros are arranged in predetermined areas in the design. For example, the I/O buffers are arranged in the I/O area and the basic cells and the macros are arranged in the gate area.
As a method of increasing the number of I/O buffers in the semiconductor integrated circuit device, various techniques are known. FIG. 1 is a plan view showing a pattern of the semiconductor integrated circuit device used in a conventional method of increasing the number of I/O buffers. Referring to FIG. 1, a chip A 101-1 where the semiconductor integrated circuit device is formed has a gate area 105-1 and a buffer area 103-1. The gate area 105-1 is provided for the center portion of the pattern for the semiconductor integrated circuit device and contains basic cells and macros. The buffer area 103-1 is provided to surround the gate area 105-1 over the whole circumferential portion of the semiconductor integrated circuit device and contains patterns for I/O buffers and pads 104. In this case, the I/O buffer patterns are arranged in the buffer area 103-1 as the circumferential portion of the chip.
When the number of I/O buffers is to be increased, the length of one side of the chip is made long, as shown in FIG. 1. That is, the chip size is made large as shown as a chip B 101-2 which has a gate area 105-2 and a buffer area 103-2. At this time, when the gate size is small, a dead space increases in the gate area 105-2.
In conjunction with the above description, a semiconductor integrated circuit device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-171756). The semiconductor integrated circuit device of this conventional example has a gate area provided for the center portion of a semiconductor substrate and a buffer area provided in the circumferential portion of the semiconductor substrate. The buffer area is divided into a plurality of buffer area portions along the circumference, and two of the buffer area portions are separated by a predetermined distance. FIG. 2 is a plan view showing the pattern of the semiconductor integrated circuit device of this conventional example. Referring to FIG. 2, a chip 111 where the semiconductor integrated circuit device is formed has a gate area 115 and a buffer area which are connected by signal lines 112. The buffer area has a plurality of buffer portions, each of which is separated into groups 113. The buffer areas portions 113 are provided in the outermost circumferential buffer area portion of the chip 111 without any space and patterns of many I/O buffers are arranged in a line in the buffer area portions 113. This technique has a purpose of increasing the number of I/O buffers which can be arranged in the same substrate area or reducing the substrate area. However, when the plurality of buffer area portions for the I/O buffers are arranged to increase the number of the I/O buffers, the buffer area portions 113 in the inner circumferential portion expands and the area usable for the gate area 115 reduces.
Also, “I/O floorplanning Guide for SA-12” (International Business Machines Corporation, ASIC Products Application Note No. SA14-2309-00, 1998) is known. FIG. 3 is a schematic plan view showing a pattern for a semiconductor integrated circuit device of this conventional example. The semiconductor integrated circuit device pattern has area I/Os 126 arranged in a matrix and gate areas 125 provided between the rows of the area I/Os 126 on a chip 121 for the semiconductor integrated circuit device. The chip 121 is for a flip chip, and does not have to provide I/O buffers in the circumferential portion. The chip 121 uses the area I/Os 126 as the I/O buffers provided in the area. A possible arrangement area of the area I/Os 126 is predetermined, and the number of I/O buffers is increased if necessary.
As described above, an area in which the area I/Os 126 can be arranged is limited. Therefore, in case that a large macro is arranged when the number of the I/O buffers is increased, the area I/Os 126 must be reduced. Therefore, the number of signals possible to be process corresponding to the number of I/O buffers is reduced. Also, it is necessary to arrange a basic cell in a little distance from the I/O buffer in consideration of influences such as latch up when the basic cell is arranged in the neighborhood of the I/O buffer. Therefore, when all the I/O buffers are arranged in the area I/Os 126, a dead space increases and the gate area 125 decreases.